Created by: Yung-Hsiang Lu, Nik Tuzov, Sunitha Jenarius.

In this project we simulate a simple processor consisting of
three consecutive parts: Fetcher, Decoder and Executer. Part1 simulates
an unpipelined processor: the next instruction is fetched only
after the current one finishes execution. Part2 simulates 
a pipelined processor: an instruction is fetched while the previous
instruction is being decoded.

The C++ code is not commented much, but UML diagrams are attached
instead.

How to run Part1 and Part2:

1) A sample set of instructions is located in file sampleprog1.
   The corresponding binary file is sampleprog1.bin which was
   created using a Perl program translator.pl supplied by our
   instructor. Attention: the simulated processor has 4 bits
   in Part1 and 6 bits in Part2 and overflows are ignored.

2) You have to use a UNIX-based machine to run the program.
   In particular, MS Visual C++ is not going to work.
   
   The executable file called simulator already exists. 
   To run the simulation, enter the part1 or part2 directory
   and type
   
   > simulator sampleprog1.bin   
    
     or

   > ./simulator sampleprog1.bin    
    
   To re-compile the C++ source files, type

   > make

   If make doesn't work, try deleting all *.o files
   first.

  
